1. Field of the Invention
This invention relates to a data holding circuit suitable for use in a microcomputer or the like and capable of being controlled by a clock signal and a control signal, outputting a signal corresponding to an input data signal, and holding it therein.
2. Description of the Related Art
A data transfer circuit is one of a type of circuit wherein data inputted to a microcomputer and data to be outputted from the microcomputer are temporarily stored therein, and signals having potential levels corresponding to information about the stored data are outputted therefrom as data and held therein. Owing to the provision of the data transfer circuit, each signal wiring or interconnection used for the transmission of data and the time interval during which each internal circuit built in the microcomputer is used for transferring data can be shortened. Further, the data can be transferred to the corresponding internal circuit to be received with good timing.
Since the data transfer circuit stores the data with satisfactory timing and transfers it therefrom, it is controlled by a clock signal and a control signal. Namely, the data transfer circuit is controlled over its operation in response to a signal for permitting the storage of data, which is used as the control signal, and stores the data in synchronism with the transition of a potential level in a predetermined direction like the falling edge of the clock signal or the rising edge thereof.
In order to provide the high-speed operation which has been desired in recent years, a microcomputer further divides the frequency of an input clock signal (called a normally-used clock signal herein) inside the microcomputer to generate such a high-speed clock signal so as to take one cycle in a 1/n cycle (where n is a positive integer greater than 2) of the normally-used clock signal, and operates its each internal circuit in synchronism with the high-speed clock signal. Alternatively, there may be cases in which a clock signal corresponding to the high-speed clock signal is already inputted to the microcomputer.
However, when the high-speed clock signal is used, the operation of each internal circuit activated according to the high-speed clock signal is also increased by n times in the microcomputer. Therefore, power consumption incident to such an operation will increase.
It is considered that in order to meet the demands of increased operating speeds and low power consumption, the normally-used clock signal and the high-speed clock signal are selectively used in the microcomputer. Namely, the microcomputer recognizes when a high-speed operation is required and sets the mode to a high-speed mode and utilizes the high-speed clock signal for the operation of each internal circuit. When no high-speed operation is required or upon a standby state, the microcomputer sets the mode to a normal mode and uses the normally-used clock signal for the operation of each internal circuit.
However, timing provided to transfer data must be controlled closely to maintain high performance with the increasing speed of the operation of each internal circuit by the high-speed clock signal. To this end, the delay of data due to wiring resistance and capacitance of each signal interconnection must be handled in consideration of transferring the data sufficiently.
As mentioned above, the operation of the data transfer circuit is to be controlled by the clock signal and the control signal. Therefore, let""s now assume that the clock signal is selectively supplied with the low power consumption, and the clock signal is supplied so that the data is stored only when the control signal is supplied. In this case, if timing provided to transfer the control signal is delayed due to the wiring resistance and capacitance of each signal interconnection when the data transfer circuit is operated in response to the high-speed clock signal, data to be stored cannot be stored correctly. If the data transfer circuit is always operated according to the transition of the potential level of the high-speed clock signal to avoid such a problem, then this leads to interference with the acquisition of a reduction in power consumption.
The present invention aims to solve the above-described problems and implement a data transfer circuit capable of meeting the demands of increased operating speed and low power consumption.
The data transfer circuit of the present invention comprises a holding circuit having a clock terminal, a data terminal and an output terminal, the holding circuit outputting an output signal having a determined voltage level according to a voltage level of a signal inputted from said data terminal corresponding with a predetermined change of a voltage level of a signal inputted said clock signal, and holding the outputted signal, a control circuit outputting a clock control signal and a data control signal, one of the clock and data control signals having a voltage level according to said control signal and another one of the clock and data control signals having a predetermined voltage level corresponding to a instruction signal, the instruction signal instructing a first mode changing the voltage level of said clock signal during a predetermined period or a second mode changing the voltage level of said clock signal during a period shorter than thereof the first mode by the voltage level of the instruction signal, a first transfer circuit transferring a signal according to said clock signal or said control signal corresponding to the voltage level of said clock control signal to said clock terminal as a first transfer signal, and a second transfer circuit transferring a signal according to said clock signal or said control signal corresponding to the voltage level of said data control signal to said data terminal as a second transfer signal.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.